When the resistor and the fuse element are formed in the same layer in a semiconductor device in which a resistor formed of a polycrystalline silicon film and a fuse element are electrically connected in parallel, two elements have to be arranged in the same plane, causing an increase in chip area. One way to solve this problem is illustrated in FIG. 9, where increase in area is suppressed by laminating a second polycrystalline silicon film 302 on a first polycrystalline silicon film 301 via a first oxide film 202 (see, for example, Japanese Patent Laid-open Application No. JP09-246384A).
When a resistor and a fuse element are laminated in the conventional manufacturing method described in JP09-246384A, the first oxide film 202 should be thick enough for fear that cutting of the fuse element by laser may damage the resistor. A thick first oxide film 202 increases the aspect ratio at the connection between the first polycrystalline silicon film 301 and the second polycrystalline silicon film 302, making the formation of connection difficult. Though electrical connection between the first polycrystalline silicon film 301 and the second polycrystalline silicon film 302 is made through their mutual contact, there is a problem in that, when native oxide film is not sufficiently removed before the deposition of the second polycrystalline silicon film 302, satisfactory electrical connection cannot be obtained.